Radiation hardened, high speed, low power very large or large scale integrated ("VLSI/LSI") IC chips are essential to the realization of certain military and other special purpose signal and data processing systems. Among semiconductor VLSI/LSI IC technoligies under consideration for such applications are GaAs E/D-MESFETs, JFETs and HEMTs. The term E/D-MESFET is an acronym for Enhancement/Depletion-Mode Metal Semiconductor Field Effect Transistor, the term JFET is an acronym for Juntion Field Effect Transistor, and the term E/D-HEMT is an acronym for High Electron Mobility Transistor. GaAs E/D-MESFETs, JFETs and HEMTs have certain advantages over silicon semiconductor technologies that make them desirable from a design standpoint. Principally, GaAs has an electron mobility which is several times higher than that of silicon, and its electron drift velocity is also faster than that of silicon. These high-electron mobility and fast drift velocity advantages permit lower power dissipation, and enables information to be transferred at faster rates.
However, there are other factors which need to be addressed in order for GaAs VLSI/LSI IC technology to mature. For example, the gate integration of D-MESFET buffer FET logic (BFL) IC chips is severely constrained by several considerations. These considerations include excessive standby power dissipation, the voltage shift network needed to apply the proper logic level to the following gate, and the need for both positive and negative power supply voltages to operate the gate circuit. Similarly, with regard to E-MESFETs, difficulties have been experienced in the past, particularly in controlling threshold voltage and the resistence between the gate and source.
However, as these problems for E-MESFETs are overcome with improved fabrication techniques and with improved materials, E-MESFETs will be better suited to the realization of VLSI/LSI IC chips than D-MESFETs. This is because E-MESFETs exhibit much lower standby power dissipation than D-MESFETs. Indeed, the standby power dissipation of an E-MESFET DCFL is almost an order of magnitude lower than a D-MESFET BFL. Additionally, E-MESFET DCFLs do not require both positive and negative power supply voltages, as do BFLs. Rather, only a single power supply voltage is needed in order for an E-MESFET DCFL to operate in an IC chip. While the operating speed of an E-MESFET is compatible with the operating speed of a D-MESFET, the speed-power product of the gate and a level of gate integration per chip are more determinative factors when considering which of these MESFET technologies to use.
It is a principal objective of the present invention to provide an improved driver circuit for a DCFL gate circuit which employs GaAs MESFET, JFET and/or HEMT technology in a way which will achieve a significant reduction in the speed-power product of the gate. Such a lower-speed power product will allow DCFL integrated circuits to handle more data at higher speeds, enable more gates to be integrated per chip, and permit the gates to drive larger loads. For example, one of the advantages of the present invention is that the push-pull driver circuit will dissipate lower static power while maintaining approximately the same operating clock speed, or where a higher clock speed is desirable, the push-pull driver circuit will exhibit a faster operating clock speed while maintaining approximately the same static power dissipation as conventional driver circuits.
Particularly with respect to large output loads, the propagation delay time of a push-pull driver circuit in accordance with the present invention will be noticably superior to that of conventional driver circuits. Additionally, an enhanced driving capability is also achieved according to the present invention, because the buffer geometry is increased without causing a significant increase of the gate static power dissipation. It should also be noted that the push-pull driver circuit will be capable of driving a transmission line interface with other compatible IC chips.
A related circuit technique has been applied to silicon N-channel MOS and Transistor-Transistor Logic ("TTL") technologies. For example, a super buffer inverter circuit is disclosed in the "Introduction To VLSI Systems", by Carver Mead and Lynn Conway, pp. 17-18, the Addison-Wesley Publishing Co., 1980. However, the design and operational considerations for the MESFET, JFET and HEMT technologies are substantially different than those for N-channel MOS technology. For example, the power supply voltage for a MESFET circuit has to be limited to prevent D.C. current flow through the gate of the MESFET, whereas such a current flow does not have to be taken into consideration by a MOSFET circuit designer. Additionally, the speed of the operation of a MESFET is two order of magnitude faster than that of MOSFET. The logic swing voltage of a MESFET is also smaller so that noise immunity must be carefully considered.